SashaGoncharov19
51d085e865
Run the original macOS ARM64 game code on iOS: - tools/retarget.py: header-only Mach-O retargeting to an iOS dylib - platform/native: UIKit host and macOS API shims (AppKit for SDL's Cocoa backend, CoreGraphics displays, CoreAudio device, Metal device properties, Wuffs PNG decoding, Steam and peripheral stubs) - touch, overlay, iOS keyboard and hardware keyboard input - tools/build_native.py: build, sign, install, data copy, launch - docs: build guide, controls, architecture Also includes the earlier static-translation research (ARM64 -> WASM -> native) under docs/research, runtime/, tests/ and tools/. No game files are included; the build reads them from a local install.
416 lines
22 KiB
Python
416 lines
22 KiB
Python
"""Bounded A64 integer-to-WAT compiler with validated immediate control flow.
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Handles selected integer operations, NZCV arithmetic, branches, and declared
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host calls. It is not a whole-program lifter. Guest registers remain 64-bit;
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memory addresses are checked before narrowing to the 64 KiB prototype memory.
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Straight-line exports use run(ctx); CFG exports use run(ctx, instruction_budget).
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Budget exhaustion returns status 3 with partial register/memory effects; it is
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an abort, not a resumable checkpoint. Incoming NZCV is not part of this ABI.
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"""
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import struct
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class UnsupportedInstruction(ValueError):
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pass
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def signed(value, bits):
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return value - (1 << bits) if value & (1 << (bits - 1)) else value
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def const(value):
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return f"(i64.const {signed(value & ((1 << 64) - 1), 64)})"
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class Compiler:
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def __init__(self, hosts=None):
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self.hosts = hosts or {}
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self.instructions = []
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self.calls = []
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def reg(self, index, width=64, sp=False):
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value = f"(local.get ${'sp' if index == 31 else 'x' + str(index)})" if index != 31 or sp else const(0)
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return value if width == 64 else f"(i64.and {value} {const(0xffffffff)})"
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def put(self, index, value, width=64, sp=False):
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if index == 31 and not sp:
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return f"(drop {value})"
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if width == 32:
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value = f"(i64.and {value} {const(0xffffffff)})"
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return f"(local.set ${'sp' if index == 31 else 'x' + str(index)} {value})"
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def address(self, base, offset):
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return f"(i64.add {self.reg(base, sp=True)} {const(offset)})"
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def load(self, size, address):
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op = {1: 'i64.load8_u', 2: 'i64.load16_u', 4: 'i64.load32_u', 8: 'i64.load'}[size]
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return f"({op} (call $addr {address} {const(size)}))"
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def store(self, size, address, value):
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op = {1: 'i64.store8', 2: 'i64.store16', 4: 'i64.store32', 8: 'i64.store'}[size]
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return f"({op} (call $addr {address} {const(size)}) {value})"
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def arithmetic(self, rd, left, right, width, subtract, flags, sp=False):
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operation = 'sub' if subtract else 'add'
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mask = const((1 << width) - 1)
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result = [f'(local.set $a {left})', f'(local.set $b {right})',
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f'(local.set $result (i64.and (i64.{operation} (local.get $a) (local.get $b)) {mask}))']
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if flags:
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a, b, r = '(local.get $a)', '(local.get $b)', '(local.get $result)'
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overflow = f'(i64.and (i64.xor {a} {b}) (i64.xor {a} {r}))' if subtract else \
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f'(i64.and (i64.xor {a} {r}) (i64.xor {b} {r}))'
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result += [f'(local.set $n (i32.wrap_i64 (i64.shr_u {r} {const(width-1)})))',
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f'(local.set $z (i64.eqz {r}))',
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f'(local.set $c (i64.{"ge_u" if subtract else "lt_u"} {a if subtract else r} {b if subtract else a}))',
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f'(local.set $v (i32.wrap_i64 (i64.shr_u {overflow} {const(width-1)})))']
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result.append(self.put(rd, '(local.get $result)', width, sp=sp and not flags))
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return result
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def condition(self, cond):
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n, z, c, v = ['(local.get $' + name + ')' for name in ('n', 'z', 'c', 'v')]
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conditions = [z, c, n, v, f'(i32.and {c} (i32.eqz {z}))',
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f'(i32.eq {n} {v})', f'(i32.and (i32.eq {n} {v}) (i32.eqz {z}))', '(i32.const 1)']
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result = conditions[cond >> 1]
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return f'(i32.eqz {result})' if cond & 1 and cond < 14 else result
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def decode(self, word, pc):
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rd, rn = word & 31, (word >> 5) & 31
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width = 64 if word >> 31 else 32
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if word == 0xd65f03c0:
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return ["(br $done)"], 'ret'
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# Narrow 128-bit load/store copy idiom; compile() validates the adjacent
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# matching pair and forbids control-flow entry into its store half.
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if word & 0xffe00c00 == 0x3cc00000:
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address = self.address(rn, signed((word >> 12) & 511, 9))
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return [f'(local.set $base {address})',
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f'(local.set $qlo {self.load(8, "(local.get $base)")})',
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f'(local.set $qhi {self.load(8, "(i64.add (local.get $base) (i64.const 8))")})'], 'copy128-load'
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if word & 0xffc00000 == 0x3d800000:
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address = self.address(rn, ((word >> 10) & 4095) * 16)
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return [f'(local.set $base {address})',
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self.store(8, '(local.get $base)', '(local.get $qlo)'),
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self.store(8, '(i64.add (local.get $base) (i64.const 8))', '(local.get $qhi)')], 'copy128-store'
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# Conditional select family (CSEL/CSINC/CSINV/CSNEG), including CSET.
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if word & 0x3fe00800 == 0x1a800000:
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rm, cond = (word >> 16) & 31, (word >> 12) & 15
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alternative = self.reg(rm, width)
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invert, increment = bool(word & (1 << 30)), bool(word & (1 << 10))
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if invert:
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alternative = f'(i64.xor {alternative} {const((1 << width)-1)})'
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if increment:
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alternative = f'(i64.add {alternative} (i64.const 1))'
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return [self.put(rd, f'(select {self.reg(rn, width)} {alternative} {self.condition(cond)})', width)], 'select-flags'
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if word & 0xfc000000 == 0x94000000:
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target = pc + signed(word & 0x3ffffff, 26) * 4
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if target not in self.hosts:
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raise UnsupportedInstruction(f"undeclared call to {target:#x}")
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host = self.hosts[target]
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self.calls.append({'site': hex(pc), 'target': hex(target), 'host': host})
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return [self.put(30, const(pc + 4)),
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f"(local.set $status (call ${host} {self.reg(0)} {self.reg(1)} {self.reg(2)}))",
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"(br_if $done (local.get $status))"], 'bl-host'
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# ADD/SUB immediate, including CMP/CMN aliases.
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if word & 0x1f000000 == 0x11000000:
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if word & (1 << 23):
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raise UnsupportedInstruction('reserved ADD/SUB immediate')
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immediate = ((word >> 10) & 4095) << (12 if word & (1 << 22) else 0)
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flags = bool(word & (1 << 29))
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return self.arithmetic(rd, self.reg(rn, width, sp=True), const(immediate), width,
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bool(word & (1 << 30)), flags, sp=True), 'arithmetic' + ('-flags' if flags else '')
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if word & 0x1f200000 == 0x0b000000:
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shift, amount = (word >> 22) & 3, (word >> 10) & 63
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if shift == 3 or amount >= width:
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raise UnsupportedInstruction('reserved arithmetic shift')
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source = self.reg((word >> 16) & 31, width)
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if shift == 2 and width == 32:
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source = f'(i64.extend_i32_u (i32.shr_s (i32.wrap_i64 {source}) (i32.const {amount})))'
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elif amount:
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source = f'(i64.{["shl", "shr_u", "shr_s"][shift]} {source} {const(amount)})'
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source = f'(i64.and {source} {const((1 << width)-1)})'
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flags = bool(word & (1 << 29))
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return self.arithmetic(rd, self.reg(rn, width), source, width,
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bool(word & (1 << 30)), flags), 'arithmetic' + ('-flags' if flags else '')
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# Move-wide immediate (MOVZ/MOVN/MOVK).
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if word & 0x1f800000 == 0x12800000:
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operation, shift = (word >> 29) & 3, ((word >> 21) & 3) * 16
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if operation == 1 or shift >= width:
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raise UnsupportedInstruction('reserved move-wide encoding')
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value = ((word >> 5) & 65535) << shift
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if operation == 0:
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expression = const((~value) & ((1 << width) - 1))
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elif operation == 2:
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expression = const(value)
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else:
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mask = (~(65535 << shift)) & ((1 << width) - 1)
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expression = f"(i64.or (i64.and {self.reg(rd, width)} {const(mask)}) {const(value)})"
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return [self.put(rd, expression, width)], 'move-wide'
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# Logical shifted register, including the MOV register alias.
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if word & 0x1f000000 == 0x0a000000:
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op, shift_kind = (word >> 29) & 3, (word >> 22) & 3
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amount, rm = (word >> 10) & 63, (word >> 16) & 31
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if op == 3 or shift_kind == 2 or amount >= width:
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raise UnsupportedInstruction('flag-setting, arithmetic shift, or reserved logical encoding')
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source = self.reg(rm, width)
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if amount:
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if shift_kind == 3 and width == 32:
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source = f"(i64.extend_i32_u (i32.rotr (i32.wrap_i64 {source}) (i32.const {amount})))"
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else:
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shift = {0: 'shl', 1: 'shr_u', 3: 'rotr'}[shift_kind]
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source = f"(i64.{shift} {source} {const(amount)})"
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if word & (1 << 21):
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source = f"(i64.xor {source} {const((1 << width) - 1)})"
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operation = {0: 'and', 1: 'or', 2: 'xor'}[op]
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return [self.put(rd, f"(i64.{operation} {self.reg(rn, width)} {source})", width)], 'logical-register'
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# Unsigned bitfield. Covers UBFX, UBFIZ and immediate logical shifts.
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if word & 0x7f800000 == 0x53000000:
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if ((word >> 22) & 1) != (width == 64):
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raise UnsupportedInstruction('reserved UBFM width')
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r, s = (word >> 16) & 63, (word >> 10) & 63
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if max(r, s) >= width:
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raise UnsupportedInstruction('reserved UBFM range')
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value = self.reg(rn, width)
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if s >= r:
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value = f"(i64.and (i64.shr_u {value} {const(r)}) {const((1 << (s - r + 1)) - 1)})"
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else:
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value = f"(i64.shl (i64.and {value} {const((1 << (s + 1)) - 1)}) {const(width - r)})"
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return [self.put(rd, value, width)], 'unsigned-bitfield'
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# Integer load/store with unsigned scaled immediate.
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if word & 0x3b000000 == 0x39000000 and not word & (1 << 26):
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size, op = 1 << (word >> 30), (word >> 22) & 3
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if op not in (0, 1):
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raise UnsupportedInstruction('signed/prefetch load variant')
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address = self.address(rn, ((word >> 10) & 4095) * size)
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code = self.put(rd, self.load(size, address)) if op else self.store(size, address, self.reg(rd))
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return [code], ('load' if op else 'store') + str(size * 8)
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# Integer unscaled or pre/post-indexed immediate accesses.
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if word & 0x3b200000 == 0x38000000 and not word & (1 << 26):
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size, op, mode = 1 << (word >> 30), (word >> 22) & 3, (word >> 10) & 3
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if op not in (0, 1) or mode == 2:
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raise UnsupportedInstruction('signed/prefetch/unprivileged unscaled access')
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if mode in (1, 3) and rn != 31 and rn == rd:
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raise UnsupportedInstruction('unscaled access with unpredictable writeback overlap')
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offset = signed((word >> 12) & 511, 9)
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result = []
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if mode == 3:
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result.append(self.put(rn, self.address(rn, offset), sp=True))
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result.append(f'(local.set $base {self.address(rn, offset if mode == 0 else 0)})')
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address = '(local.get $base)'
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result.append(self.put(rd, self.load(size, address)) if op else self.store(size, address, self.reg(rd)))
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if mode == 1:
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result.append(self.put(rn, self.address(rn, offset), sp=True))
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return result, 'unscaled-access'
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# Integer pairs, including SP pre/post-indexed stack saves.
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if word & 0x3a000000 == 0x28000000 and not word & (1 << 26):
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opc, mode, rt2 = word >> 30, (word >> 23) & 3, (word >> 10) & 31
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if opc not in (0, 2) or mode == 0:
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raise UnsupportedInstruction('non-temporal/signed/reserved pair')
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if mode in (1, 3) and rn != 31 and rn in (rd, rt2):
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raise UnsupportedInstruction('pair with constrained-unpredictable writeback overlap')
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size = 8 if opc == 2 else 4
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offset = signed((word >> 15) & 127, 7) * size
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result = []
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if mode == 3:
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result.append(self.put(rn, self.address(rn, offset), sp=True))
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effective_offset = offset if mode == 2 else 0
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# Snapshot the base so register destinations cannot alter later addresses.
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result.append(f"(local.set $base {self.address(rn, effective_offset)})")
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for index, register in enumerate((rd, rt2)):
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address = f"(i64.add (local.get $base) {const(index * size)})"
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if word & (1 << 22):
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result.append(self.put(register, self.load(size, address)))
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else:
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result.append(self.store(size, address, self.reg(register)))
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if mode == 1:
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result.append(self.put(rn, self.address(rn, offset), sp=True))
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return result, ('load' if word & (1 << 22) else 'store') + '-pair'
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raise UnsupportedInstruction(f"unsupported opcode 0x{word:08x}")
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def compile(self, body, address):
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self.instructions = []
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self.calls = []
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if not body or len(body) % 4:
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raise ValueError('A64 input must contain complete instructions')
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words = list(struct.unpack('<' + 'I' * (len(body) // 4), body))
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for i, word in enumerate(words):
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if word & 0xffe00c00 == 0x3cc00000:
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if i + 1 >= len(words) or words[i+1] & 0xffc0001f != 0x3d800000 | (word & 31):
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raise UnsupportedInstruction('128-bit load requires adjacent matching store')
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if word & 0xffc00000 == 0x3d800000:
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if not i or words[i-1] & 0xffe00c1f != 0x3cc00000 | (word & 31):
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raise UnsupportedInstruction('128-bit store requires adjacent matching load')
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for j, candidate in enumerate(words):
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branch = self.branch(candidate, address+j*4)
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if branch and branch[0] == address+i*4:
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raise UnsupportedInstruction('control flow enters 128-bit copy halfway')
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if any(self.branch(word, address + i * 4) is not None for i, word in enumerate(words)):
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return self.compile_cfg(words, address)
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code = []
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saw_ret = False
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defined_flags = False
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for index, (word,) in enumerate(struct.iter_unpack('<I', body)):
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pc = address + index * 4
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if saw_ret:
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raise UnsupportedInstruction('bytes after terminal RET require a control-flow model')
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try:
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emitted, kind = self.decode(word, pc)
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except UnsupportedInstruction as error:
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raise UnsupportedInstruction(f'{pc:#x}: {error}') from error
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if kind == 'select-flags' and ((word >> 12) & 15) < 14 and not defined_flags:
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raise UnsupportedInstruction(f'conditional select reads undefined NZCV at {pc:#x}')
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if kind == 'arithmetic-flags':
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defined_flags = True
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elif kind == 'bl-host':
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defined_flags = False
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self.instructions.append({'address': hex(pc), 'word': f'{word:08x}', 'kind': kind})
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code += [f';; {pc:#x}: {word:08x} {kind}', *emitted]
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saw_ret = kind == 'ret'
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if not saw_ret:
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raise UnsupportedInstruction('missing terminal RET')
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registers = [f'x{i}' for i in range(31)] + ['sp']
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imports = '\n'.join(f'(import "env" "{name}" (func ${name} (param i64 i64 i64) (result i32)))'
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for name in sorted(set(self.hosts.values())))
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declarations = '\n'.join(f'(local ${name} i64)' for name in registers)
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loads = '\n'.join(f'(local.set ${name} (i64.load offset={i * 8} (local.get $ctx)))'
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for i, name in enumerate(registers))
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stores = '\n'.join(f'(i64.store offset={i * 8} (local.get $ctx) (local.get ${name}))'
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for i, name in enumerate(registers))
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return f'''(module
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{imports}
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(memory (export "memory") 1 1)
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(func $addr (param $value i64) (param $size i64) (result i32)
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(if (i64.gt_u (local.get $value) (i64.sub (i64.const 65536) (local.get $size)))
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(then unreachable))
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(i32.wrap_i64 (local.get $value)))
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(func (export "run") (param $ctx i32) (result i32)
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{declarations}
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(local $base i64) (local $status i32)
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(local $a i64) (local $b i64) (local $result i64) (local $qlo i64) (local $qhi i64)
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(local $n i32) (local $z i32) (local $c i32) (local $v i32)
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{loads}
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(block $done
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{chr(10).join(code)}
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)
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{stores}
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(local.get $status)))
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'''
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def branch(self, word, pc):
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"""Return (target, condition) for supported immediate branches."""
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if word & 0xfc000000 == 0x14000000:
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return pc + signed(word & 0x3ffffff, 26) * 4, None
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if word & 0xff000010 == 0x54000000:
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cond = word & 15
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return pc + signed((word >> 5) & 0x7ffff, 19) * 4, self.condition(cond)
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if word & 0x7e000000 == 0x34000000:
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width = 64 if word >> 31 else 32
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zero = f'(i64.eqz {self.reg(word & 31, width)})'
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condition = f'(i32.eqz {zero})' if word & (1 << 24) else zero
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return pc + signed((word >> 5) & 0x7ffff, 19) * 4, condition
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if word & 0x7e000000 == 0x36000000:
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bit = ((word >> 31) << 5) | ((word >> 19) & 31)
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zero = f'(i64.eqz (i64.and {self.reg(word & 31)} {const(1 << bit)}))'
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condition = f'(i32.eqz {zero})' if word & (1 << 24) else zero
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return pc + signed((word >> 5) & 0x3fff, 14) * 4, condition
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return None
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def compile_cfg(self, words, address):
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"""Validated instruction-block dispatcher; guest loops consume a caller budget.
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Each instruction is currently a block. This deliberately simple CFG is
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correct before block coalescing/structured-loop optimization is added.
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"""
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end = address + len(words) * 4
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nodes = []
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reachable = set()
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successors = {}
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pending = [address]
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while pending:
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pc = pending.pop()
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if pc in reachable:
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continue
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if not address <= pc < end or (pc - address) % 4:
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raise UnsupportedInstruction(f'control flow outside declared body: {pc:#x}')
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reachable.add(pc)
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word = words[(pc - address) // 4]
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branch = self.branch(word, pc)
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if branch:
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edges = [branch[0]]
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if branch[1] is not None:
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edges.append(pc + 4)
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elif word != 0xd65f03c0:
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edges = [pc + 4]
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else:
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edges = []
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successors[pc] = edges
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pending.extend(edges)
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if len(reachable) != len(words):
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raise UnsupportedInstruction('unreachable bytes require explicit code/data classification')
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if not any(word == 0xd65f03c0 for word in words):
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raise UnsupportedInstruction('missing RET in control-flow body')
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for i, word in enumerate(words):
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pc = address + i * 4
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branch = self.branch(word, pc)
|
|
if branch:
|
|
target, condition = branch
|
|
next_pc = f'(i32.const {(target-address)//4})'
|
|
if condition is not None:
|
|
next_pc = f'(select {next_pc} (i32.const {i+1}) {condition})'
|
|
emitted = [f'(local.set $pc {next_pc})', '(br $dispatch)']
|
|
kind = 'branch-immediate'
|
|
else:
|
|
emitted, kind = self.decode(word, pc)
|
|
emitted += [f'(local.set $pc (i32.const {i+1}))', '(br $dispatch)']
|
|
self.instructions.append({'address': hex(pc), 'word': f'{word:08x}', 'kind': kind})
|
|
nodes.append(f'(if (i32.eq (local.get $pc) (i32.const {i})) (then\n' + '\n'.join(emitted) + '\n))')
|
|
# Require flags to be defined on every path before a conditional read.
|
|
# Host calls invalidate flags: their ARM64 ABI does not preserve NZCV.
|
|
incoming = {pc: pc != address for pc in reachable}
|
|
outgoing = dict(incoming)
|
|
changed = True
|
|
while changed:
|
|
changed = False
|
|
for i, instruction in enumerate(self.instructions):
|
|
pc = address + i * 4
|
|
predecessors = [p for p, edges in successors.items() if pc in edges]
|
|
value = pc != address and all(outgoing[p] for p in predecessors)
|
|
after = True if instruction['kind'] == 'arithmetic-flags' else \
|
|
False if instruction['kind'] == 'bl-host' else value
|
|
if (incoming[pc], outgoing[pc]) != (value, after):
|
|
incoming[pc], outgoing[pc] = value, after
|
|
changed = True
|
|
for i, word in enumerate(words):
|
|
cond = (word & 15) if word & 0xff000010 == 0x54000000 else \
|
|
((word >> 12) & 15) if self.instructions[i]['kind'] == 'select-flags' else 14
|
|
if cond < 14 and not incoming[address+i*4]:
|
|
raise UnsupportedInstruction(f'conditional operation reads undefined NZCV at {address+i*4:#x}')
|
|
registers = [f'x{i}' for i in range(31)] + ['sp']
|
|
imports = '\n'.join(f'(import "env" "{name}" (func ${name} (param i64 i64 i64) (result i32)))'
|
|
for name in sorted(set(self.hosts.values())))
|
|
declarations = '\n'.join(f'(local ${name} i64)' for name in registers)
|
|
loads = '\n'.join(f'(local.set ${name} (i64.load offset={i * 8} (local.get $ctx)))'
|
|
for i, name in enumerate(registers))
|
|
stores = '\n'.join(f'(i64.store offset={i * 8} (local.get $ctx) (local.get ${name}))'
|
|
for i, name in enumerate(registers))
|
|
return f'''(module
|
|
{imports}
|
|
(memory (export "memory") 1 1)
|
|
(func $addr (param $value i64) (param $size i64) (result i32)
|
|
(if (i64.gt_u (local.get $value) (i64.sub (i64.const 65536) (local.get $size))) (then unreachable))
|
|
(i32.wrap_i64 (local.get $value)))
|
|
(func (export "run") (param $ctx i32) (param $budget i32) (result i32)
|
|
{declarations}
|
|
(local $base i64) (local $status i32) (local $pc i32)
|
|
(local $a i64) (local $b i64) (local $result i64) (local $qlo i64) (local $qhi i64)
|
|
(local $n i32) (local $z i32) (local $c i32) (local $v i32)
|
|
{loads}
|
|
(block $done
|
|
(loop $dispatch
|
|
(if (i32.eqz (local.get $budget)) (then (local.set $status (i32.const 3)) (br $done)))
|
|
(local.set $budget (i32.sub (local.get $budget) (i32.const 1)))
|
|
{chr(10).join(nodes)}
|
|
unreachable
|
|
))
|
|
{stores}
|
|
(local.get $status)))
|
|
'''
|